1. Field of the Invention
The invention relates in general to a phase-locked loop (PLL) and more particularly to a method for calibrating a PLL.
2. Description of the Related Art
In current computer systems and communication systems, a phase-locked loop (PLL) providing oscillation signals of accurate frequencies plays a crucial role. Taking a wireless communication system for example, its transmission end often utilizes oscillation signals generated by a PLL as a reference for signal transmission. As a result, the quality of wireless signals is directly influenced by characteristics from a locking speed, a loop bandwidth to surge energy of the PLL.
FIG. 1 shows a structural diagram of a type-I phased-locked loop. A PLL 10 comprises a phase detector 11, a charge pump 12, a filter 13 consisted of a resistor R and a capacitor C, a voltage-controlled oscillator (VCO) 14, and a frequency divider 15. Since the resistor R forms a leakage path between an input end and a ground end of the VCO 14, the phase detector 11 is mandated to output cyclic pulses whether the PLL 10 is locked, so that the charge pump 12 charges the input end of the VCO 14 to compensate charge lost through the resistor R. When the PLL 10 is stabilized and a balance between charging and discharging is reached, a cycle of the pulses then equals a cycle of reference signals. However, the existence of the cyclic pulses imposes interference on oscillation signals at the output end of the VCO 14. As a phase difference between the reference signals and feedback signals grows larger, the pulses become wider and have greater energy. Consider circumstances that the oscillation signals have a frequency of 3.66 GHz, and the reference signals have a frequency of 26 MHz. In a spectrum of the output signals from the VCO 14, apart from a main component occurring at 3.66 GHz, so-called surges at 3.66 GHz±26 MHz are also present. Many wireless communication standards have specifications regarding upper limits of surge energy. A shortcoming of the type-I PLL is that the charging pulses usually result in excessively high surge energy.
FIG. 2 shows a structural diagram of a type-II PLL. A PLL 20 comprises a phase detector 21, two charge pumps 22A and 22B, an active filter 23 consisted of a resistor R, capacitors C1, C2 and C3, and an amplifier 23A, a VCO 24, and a frequency divider 25. As the PLL 20 becomes locked from unlocked, the second charge pump 22B charges/discharges the capacitor C1 in the active filter 23 according to a phase difference detected by the phase detector 21, until a reference voltage VREF indicated in the diagram is gradually pulled up/down to a control voltage appropriate for an input end of the VCO 24 when the PLL 20 is locked. Before the PLL 20 becomes locked, the reference voltage VREF and the control voltage usually need to go through a period of damping to be stabilized. This structure is free from the excessively high surge energy occurring in the type-I PLL, but yet a locking speed of the PLL 20 is directly restrained by a charge/discharge speed of the second charge pump 22B with respect to the capacitor C1. Further, the damping process also lengthens the locking speed of the PLL 20.
In addition, regardless the type of the abovementioned PLLs implemented, their parameters are shifted by a certain degree due to ambient variants from manufacture, temperature to voltage factors, such that many characteristics (e.g., bandwidth) do not match with predetermined values originally hoped to achieve at the time of designing the PLL.